forked from github/verilator
172 lines
3.8 KiB
Systemverilog
172 lines
3.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg [2:0] value;
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reg [31:0] rglobal;
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reg [31:0] vec [1:0];
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reg [31:0] n;
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int abcd;
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initial begin
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rglobal = 1;
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value = 2;
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if (add(value) != 3'd3) $stop;
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if (rglobal != 2) $stop;
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if (add(add(3'd1)) != 3'd3) $stop;
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if (rglobal != 4) $stop;
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if (munge4(4'b0010) != 4'b1011) $stop;
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if (toint(2) != 3) $stop;
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if (rglobal != 5) $stop;
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setit;
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incr(rglobal,rglobal,32'h10);
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if (rglobal != 32'h17) $stop;
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nop(32'h11);
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empty;
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empty();
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rglobal = 32'h00000001;
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flipupperbit(rglobal,4'd4);
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flipupperbit(rglobal,4'd12);
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if (rglobal !== 32'h10100001) $stop;
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if (nil_func(32'h12,32'h12) != 32'h24) $stop;
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nil_task(32'h012,32'h112,rglobal);
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if (rglobal !== 32'h124) $stop;
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vec[0] = 32'h333;
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vec[1] = 32'habc;
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incr(vec[1],vec[0],vec[1]);
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if (vec[0] != 32'h333) $stop;
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if (vec[1] != 32'hdef) $stop;
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// verilator lint_off SELRANGE
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incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector!
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// verilator lint_on SELRANGE
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n=1;
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nil();
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if (n !== 10) $stop;
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// Functions called as tasks
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// verilator lint_off IGNOREDRETURN
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rglobal = 32'h4;
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if (inc_and_return(32'h2) != 32'h6) $stop;
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if (rglobal !== 32'h6) $stop;
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rglobal = 32'h6;
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inc_and_return(32'h3);
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if (rglobal !== 32'h9) $stop;
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// verilator lint_on IGNOREDRETURN
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abcd = 0;
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set_1_to_abcd;
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if (abcd != 1) $stop;
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set_2_to_abcd;
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if (abcd != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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function [2:0] add;
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input [2:0] fromv;
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begin
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add = fromv + 3'd1;
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begin : named
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reg [31:0] flocal;
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flocal = 1;
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rglobal = rglobal + flocal;
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end : named // SystemVerilog end labels
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end
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endfunction
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function [3:0] munge4;
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input [3:0] fromv; // Different fromv than the 'fromv' signal above
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reg one;
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begin : named
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reg [1:0] flocal;
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// Function calling a function
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one = 1'b1;
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munge4 = {one, add(fromv[2:0])};
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end
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endfunction
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task setit;
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reg [31:0] temp;
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begin
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temp = rglobal + 32'h1;
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rglobal = temp + 32'h1;
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end
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endtask
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task incr (
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// Check a V2K style input/output list
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output [31:0] z,
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input [31:0] a, inc
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);
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z = a + inc;
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endtask
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task nop;
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input [31:0] a;
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begin
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end
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endtask
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task empty;
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endtask
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task flipupperbit;
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inout [31:0] vector;
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input [3:0] bitnum;
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reg [4:0] bitnum2;
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begin
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bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation
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vector[bitnum2] = vector[bitnum2] ^ 1'b1;
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end
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endtask
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task nil_task;
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input [31:0] a;
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input [31:0] b;
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output [31:0] q;
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// verilator no_inline_task
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q = nil_func(a, b);
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endtask
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function void nil;
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n = 10;
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endfunction
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function [31:0] nil_func;
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input [31:0] fa;
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input [31:0] fb;
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// verilator no_inline_task
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nil_func = fa + fb;
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endfunction
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function integer toint;
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input integer fa;
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toint = fa + 32'h1;
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endfunction
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function [31:0] inc_and_return;
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input [31:0] inc;
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rglobal = rglobal + inc;
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return rglobal;
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endfunction
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function void set_1_to_abcd;
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abcd = 1;
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endfunction
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task set_2_to_abcd;
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abcd = 2;
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endtask
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endmodule
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