forked from github/verilator
38 lines
1.2 KiB
Systemverilog
38 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2020 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t_format_wide_decimal(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cycle = 0;
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bit [1023:0] x = '1;
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always @(posedge clk) begin
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if (cycle == 0) begin
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// Format very wide constant number (which has more bits than can
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// be counted in exponent of a double precision float), with %d.
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$display("%d", 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff);
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end else begin
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// Same, but for a variable with value only known at run-time
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$display("%d", x);
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end
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cycle <= cycle + 1;
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x <= x >> 1;
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if (cycle == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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