forked from github/verilator
47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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class Cls;
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int q[$];
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function new();
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q.push_back(1);
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q.push_back(2);
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q.push_back(3);
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endfunction
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endclass
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module t (/*AUTOARG*/);
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int two[5:6];
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if (1) begin : named
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Cls c;
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end
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function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d);
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crc = {sum[62:0],sum[63]} ^ {20'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]};
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endfunction
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bit [63:0] sum;
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initial begin
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named.c = new;
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sum = 0;
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foreach (named.c.q[i]) begin
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foreach (two[j]) begin
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// $display(i, j);
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sum = crc(sum, i, named.c.q[i], j, 0);
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end
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end
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`checkh(sum, 64'h000000a02d0fc000);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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