forked from github/verilator
58 lines
1.4 KiB
Systemverilog
58 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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sub sub();
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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// procedural var sub.subvar
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if (cyc == 50) begin
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`checkh(sub.subvar, 32'h666);
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force sub.subvar = 32'hffff;
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end
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else if (cyc == 51) begin
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`checkh(sub.subvar, 32'hffff);
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sub.subvar = 32'h543; // Ignored as still forced
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end
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else if (cyc == 52) begin
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`checkh(sub.subvar, 32'hffff);
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end
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else if (cyc == 53) begin
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release sub.subvar;
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end
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else if (cyc == 54) begin
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`checkh(sub.subvar, 32'hffff); // Retains value until next procedural change
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sub.subvar = 32'h544;
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end
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else if (cyc == 56) begin
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`checkh(sub.subvar, 32'h544);
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end
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//
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub;
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int subvar;
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initial subvar = 32'h666;
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endmodule
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