forked from github/verilator
539c9d4c63
- Add more tests, including for tracing. - Apply some cleaner, more generic abstractions in the implementation. - Use clearer AstRelease which is not an assignment.
131 lines
3.2 KiB
Systemverilog
131 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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always @(posedge clk) cyc <= cyc + 1;
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wire net_1;
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wire [7:0] net_8;
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assign net_1 = ~cyc[0];
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assign net_8 = ~cyc[1 +: 8];
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always @ (posedge clk) begin
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$display("%d pre : %x %x", cyc, net_8, net_1);
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case (cyc)
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4: begin
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`checkh (net_1, 0);
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`checkh (net_8, ~cyc[1 +: 8]);
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end
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5: begin
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`checkh (net_1, 0);
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`checkh (net_8, 8'h5f);
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end
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6: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'h5f);
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end
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7, 8: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'hf5);
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end
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9: begin
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`checkh (net_1, ~cyc[0]);
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`checkh (net_8, 8'hf5);
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end
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11, 12: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'h5a);
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end
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13, 14: begin
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`checkh (net_1, 0);
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`checkh (net_8, 8'ha5);
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end
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default: begin
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`checkh ({net_8, net_1}, ~cyc[0 +: 9]);
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end
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endcase
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`ifndef REVERSE
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if (cyc == 3) force net_1 = 0;
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if (cyc == 5) force net_1 = 1;
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if (cyc == 8) release net_1;
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if (cyc == 4) force net_8 = 8'h5f;
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if (cyc == 6) force net_8 = 8'hf5;
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if (cyc == 9) release net_8;
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if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010;
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if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0;
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if (cyc == 14) release {net_1, net_8};
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`else
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if (cyc == 8) release net_1;
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if (cyc == 5) force net_1 = 1;
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if (cyc == 3) force net_1 = 0;
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if (cyc == 9) release net_8;
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if (cyc == 6) force net_8 = 8'hf5;
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if (cyc == 4) force net_8 = 8'h5f;
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if (cyc == 14) release {net_1, net_8};
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if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0;
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if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010;
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`endif
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$display("%d post: %x %x", cyc, net_8, net_1);
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case (cyc)
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3: begin
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`checkh (net_1, 0);
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`checkh (net_8, ~cyc[1 +: 8]);
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end
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4: begin
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`checkh (net_1, 0);
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`checkh (net_8, 8'h5f);
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end
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5: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'h5f);
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end
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6, 7: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'hf5);
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end
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8: begin
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`checkh (net_1, ~cyc[0]);
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`checkh (net_8, 8'hf5);
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end
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10, 11: begin
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`checkh (net_1, 1);
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`checkh (net_8, 8'h5a);
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end
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12, 13: begin
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`checkh (net_1, 0);
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`checkh (net_8, 8'ha5);
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end
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default: begin
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`checkh ({net_8, net_1}, ~cyc[0 +: 9]);
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end
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endcase
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if (cyc == 30) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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