forked from github/verilator
118 lines
3.1 KiB
Systemverilog
118 lines
3.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] cyc; initial cyc = 0;
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reg [31:0] loops;
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reg [31:0] loops2;
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integer i;
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always @ (posedge clk) begin
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cyc <= cyc+8'd1;
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if (cyc == 8'd1) begin
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$write("[%0t] t_loop: Running\n", $time);
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// Unwind <
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loops = 0;
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loops2 = 0;
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for (i=0; i<16; i=i+1) begin
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loops = loops + i; // surefire lint_off_line ASWEMB
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loops2 = loops2 + i; // surefire lint_off_line ASWEMB
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end
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if (i !== 16) $stop;
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if (loops !== 120) $stop;
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if (loops2 !== 120) $stop;
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// Unwind <=
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loops = 0;
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for (i=0; i<=16; i=i+1) begin
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loops = loops + 1;
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end
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if (i !== 17) $stop;
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if (loops !== 17) $stop;
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// Don't unwind breaked loops
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loops = 0;
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for (i=0; i<16; i=i+1) begin
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loops = loops + 1;
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if (i==7) i=99; // break out of loop
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end
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if (loops !== 8) $stop;
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// Don't unwind large loops!
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loops = 0;
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for (i=0; i<100000; i=i+1) begin
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loops = loops + 1;
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end
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if (loops !== 100000) $stop;
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// Test post-increment
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loops = 0;
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for (i=0; i<=16; i++) begin
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loops = loops + 1;
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end
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if (i !== 17) $stop;
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if (loops !== 17) $stop;
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// Test pre-increment
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loops = 0;
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for (i=0; i<=16; ++i) begin
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loops = loops + 1;
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end
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if (i !== 17) $stop;
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if (loops !== 17) $stop;
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// Test post-decrement
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loops = 0;
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for (i=16; i>=0; i--) begin
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loops = loops + 1;
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end
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if (i !== -1) $stop;
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if (loops !== 17) $stop;
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// Test pre-decrement
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loops = 0;
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for (i=16; i>=0; --i) begin
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loops = loops + 1;
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end
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if (i !== -1) $stop;
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if (loops !== 17) $stop;
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//
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// 1800-2017 optionals init/expr/incr
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loops = 0;
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i = 0;
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for (; i<10; ++i) ++loops;
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if (loops !== 10) $stop;
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//
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loops = 0;
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i = 0;
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for (i=0; i<10; ) begin ++loops; ++i; end
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if (loops !== 10) $stop;
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//
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loops = 0;
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i = 0;
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for (; ; ++i) begin ++loops; break; end
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if (loops !== 1) $stop;
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//
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// bug1605
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i = 1;
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for (i=20; 0; ) ;
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if (i != 20) $stop;
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for (i=30; i<10; i++) ;
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if (i != 30) $stop;
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// Comma
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loops = 0;
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for (i=0; i<20; ++i, ++loops);
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if (loops !== 20) $stop;
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loops = 0;
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for (i=0; i<20; ++loops, ++i);
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if (loops !== 20) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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