forked from github/verilator
145 lines
4.0 KiB
Systemverilog
145 lines
4.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [3:0] l_stop = crc[3:0];
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wire [3:0] l_break = crc[7:4];
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wire [3:0] l_continue = crc[11:8];
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/*AUTOWIRE*/
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wire [15:0] out0 = Test0(l_stop, l_break, l_continue);
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wire [15:0] out1 = Test1(l_stop, l_break, l_continue);
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wire [15:0] out2 = Test2(l_stop, l_break, l_continue);
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wire [15:0] out3 = Test3(l_stop, l_break, l_continue);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out3,out2,out1,out0};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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if (out0!==out1) $stop;
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if (out0!==out2) $stop;
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if (out0!==out3) $stop;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h293e9f9798e97da0
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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function [15:0] Test0;
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input [3:0] loop_stop;
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input [3:0] loop_break;
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input [3:0] loop_continue;
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integer i;
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reg broken;
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Test0 = 0;
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broken = 0;
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begin
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for (i=1; i<20; i=i+1) begin
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if (!broken) begin
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Test0 = Test0 + 1;
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if (i[3:0] != loop_continue) begin // continue
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if (i[3:0] == loop_break) begin
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broken = 1'b1;
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end
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if (!broken) begin
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Test0 = Test0 + i[15:0];
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end
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end
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end
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end
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end
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endfunction
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function [15:0] Test1;
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input [3:0] loop_stop;
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input [3:0] loop_break;
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input [3:0] loop_continue;
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integer i;
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Test1 = 0;
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begin : outer_block
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for (i=1; i<20; i=i+1) begin : inner_block
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Test1 = Test1 + 1;
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// continue, IE jump to end-of-inner_block. Must be inside inner_block.
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if (i[3:0] == loop_continue) disable inner_block;
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// break, IE jump to end-of-outer_block. Must be inside outer_block.
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if (i[3:0] == loop_break) disable outer_block;
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Test1 = Test1 + i[15:0];
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end : inner_block
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end : outer_block
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endfunction
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function [15:0] Test2;
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input [3:0] loop_stop;
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input [3:0] loop_break;
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input [3:0] loop_continue;
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integer i;
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Test2 = 0;
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begin
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for (i=1; i<20; i=i+1) begin
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Test2 = Test2 + 1;
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if (i[3:0] == loop_continue) continue;
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if (i[3:0] == loop_break) break;
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Test2 = Test2 + i[15:0];
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end
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end
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endfunction
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function [15:0] Test3;
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input [3:0] loop_stop;
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input [3:0] loop_break;
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input [3:0] loop_continue;
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integer i;
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Test3 = 0;
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begin
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for (i=1; i<20; i=i+1) begin
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Test3 = Test3 + 1;
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if (i[3:0] == loop_continue) continue;
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// return, IE jump to end-of-function optionally setting return value
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if (i[3:0] == loop_break) return Test3;
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Test3 = Test3 + i[15:0];
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end
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end
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endfunction
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endmodule
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