forked from github/verilator
21 lines
525 B
Systemverilog
21 lines
525 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// width warnings off due to command line
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wire A = 15'd1234;
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// width warnings off due to command line + manual switch
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// verilator lint_off WIDTH
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wire B = 15'd1234;
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// this turnon does nothing as off on command line
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// verilator lint_on WIDTH
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wire C = 15'd1234;
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endmodule
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