forked from github/verilator
39 lines
636 B
Systemverilog
39 lines
636 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module a;
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c c ();
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initial begin
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$write("Bad top modules\n");
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$stop;
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end
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endmodule
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module a2;
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initial begin
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$write("Bad top modules\n");
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$stop;
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end
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endmodule
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module b;
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d d ();
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endmodule
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module c;
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initial begin
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$write("Bad mid modules\n");
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$stop;
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end
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endmodule
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module d;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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