forked from github/verilator
28 lines
579 B
Systemverilog
28 lines
579 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// issue3005
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module t #(parameter NV = 2000)
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(
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input a,
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input w1,
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input [127:0] w2,
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output [ 31:0] o,
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input [319:0] bi,
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output [319:0] bo
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);
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// verilator lint_off WIDTH
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wire [NV-1:0] d = a ? NV'(0) : {NV{w2}};
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// verilator lint_on WIDTH
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assign o = d[31:0];
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assign bo = ~bi;
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endmodule
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