forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
36 lines
1002 B
Perl
Executable File
36 lines
1002 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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sub check_evals {
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my $got = 0;
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foreach my $file (glob("$Self->{obj_dir}/*.cpp")) {
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my $fh = IO::File->new("<$file");
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local $/; undef $/;
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my $wholefile = <$fh>;
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if ($wholefile =~ /__eval_nba__[0-9]+\(.*\)\s*{/) {
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++$got;
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}
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}
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$got >= 2 or error("Too few _eval functions found: $got");
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}
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scenarios(vlt => 1);
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compile(
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v_flags2 => ["--output-split 1 --output-split-cfuncs 20"],
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verilator_make_gmake => 0, # Slow to compile, so skip it
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);
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check_evals();
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ok(1);
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1;
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