forked from github/verilator
103 lines
2.5 KiB
Systemverilog
103 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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//
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// Constants should not be shared by different non-inlined modules
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//
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module a(
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input wire clk,
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input wire trig_i,
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output reg trig_o
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);
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/* verilator no_inline_module */
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// Same constant as in module b
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wire [255:0] C = {32'h1111_1111,
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32'h2222_2222,
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32'h3333_3333,
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32'h4444_4444,
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32'h5555_5555,
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32'h6666_6666,
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32'h7777_7777,
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32'h8888_8888};
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always @(posedge clk) begin
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trig_o <= 1'd0;
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if (trig_i) begin
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// Note: Base index via $c to prevent optimizatoin by Verilator
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$display("0x%8x", C[$c(0*32)+:32]);
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$display("0x%8x", C[$c(2*32)+:32]);
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$display("0x%8x", C[$c(4*32)+:32]);
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$display("0x%8x", C[$c(6*32)+:32]);
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$display("0x%32x", C);
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trig_o <= 1'd1;
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end
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end
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endmodule
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module b(
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input wire clk,
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input wire trig_i,
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output reg trig_o
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);
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/* verilator no_inline_module */
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// Same constant as in module a
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wire [255:0] C = {32'h1111_1111,
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32'h2222_2222,
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32'h3333_3333,
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32'h4444_4444,
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32'h5555_5555,
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32'h6666_6666,
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32'h7777_7777,
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32'h8888_8888};
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always @(posedge clk) begin
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trig_o <= 1'd0;
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if (trig_i) begin
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// Note: Base index via $c to prevent optimizatoin by Verilator
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$display("0x%8x", C[$c(1*32)+:32]);
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$display("0x%8x", C[$c(3*32)+:32]);
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$display("0x%8x", C[$c(5*32)+:32]);
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$display("0x%8x", C[$c(7*32)+:32]);
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$display("0x%32x", C);
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trig_o <= 1'd1;
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end
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end
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg trig_i;
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wire trig_ab;
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wire trig_o;
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a a_inst(.clk(clk), .trig_i(trig_i), .trig_o(trig_ab));
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b b_inst(.clk(clk), .trig_i(trig_ab), .trig_o(trig_o));
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always @(posedge clk) begin
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trig_i <= cyc == 1;
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if (trig_o) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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cyc++;
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end
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endmodule
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