forked from github/verilator
60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] cyc; initial cyc = 0;
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reg [31:0] in;
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wire [31:0] out;
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t_extend_class_v sub (.in(in), .out(out));
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always @ (posedge clk) begin
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cyc <= cyc + 8'd1;
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if (cyc == 8'd1) begin
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in <= 32'h10;
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end
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if (cyc == 8'd2) begin
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if (out != 32'h11) $stop;
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end
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if (cyc == 8'd9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t_extend_class_v (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input [31:0] in;
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output logic [31:0] out;
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always @* begin
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// When "in" changes, call my method
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out = $c("this->m_myobjp->my_math(", in, ")");
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end
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`systemc_header
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#include "t_extend_class_c.h" // Header for contained object
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`systemc_interface
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t_extend_class_c* m_myobjp; // Pointer to object we are embedding
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`systemc_ctor
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m_myobjp = new t_extend_class_c(); // Construct contained object
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`systemc_dtor
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delete m_myobjp; // Destruct contained object
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`verilog
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endmodule
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