forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
77 lines
1.6 KiB
Systemverilog
77 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef TEST_VERBOSE
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`define WRITE_VERBOSE(args) $write args
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`else
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`define WRITE_VERBOSE(args)
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`endif
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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event e1;
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event e2;
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`ifndef IVERILOG
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event ev [3:0];
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`endif
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int cyc = 0;
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int last_event = 0;
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always @(e1) begin
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`WRITE_VERBOSE(("[%0t] e1\n", $time));
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if (!e1.triggered) $stop;
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last_event[1] = 1;
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end
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always @(e2) begin
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`WRITE_VERBOSE(("[%0t] e2\n", $time));
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if (!e2.triggered) $stop;
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last_event[2] = 1;
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end
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always @(posedge clk) begin
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`WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event));
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cyc <= cyc + 1;
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case (cyc)
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default: begin
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// Check no initial or spurious trigger
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if (last_event != 0) $stop;
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end
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//
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10: begin
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if (last_event != 0) $stop;
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-> e1;
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if (!e1.triggered) $stop;
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end
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11: begin
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if (last_event != 32'b10) $stop;
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last_event = 0;
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end
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//
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13: begin
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if (last_event != 0) $stop;
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->> e2;
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if (e2.triggered) $stop;
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end
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14: begin
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if (last_event != 32'b100) $stop;
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last_event = 0;
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end
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//
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99: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endcase
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end
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endmodule
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