forked from github/verilator
25 lines
472 B
Systemverilog
25 lines
472 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Jonathon Donaldson.
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// SPDX-License-Identifier: CC0-1.0
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// bug855
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module our;
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typedef enum logic {n,N} T_Flg_N;
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typedef struct packed {
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T_Flg_N N;
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} T_PS_Reg;
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T_PS_Reg PS = 1'b1;
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initial begin
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$write ("P:%s\n", PS.N.name);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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