forked from github/verilator
78 lines
2.0 KiB
Systemverilog
78 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef enum logic [59:0] {
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E01 = 60'h1,
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ELARGE = 60'h1234_4567_abcd
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} my_t;
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integer cyc = 0;
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my_t e;
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string all;
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int i_cast;
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// Check runtime
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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// Setup
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e <= E01;
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end
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else if (cyc == 1) begin
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`checks(e.name, "E01");
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`checkh(e.next, ELARGE);
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`checkh(e.next(0), E01);
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`checkh(e.prev(0), E01);
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e <= ELARGE;
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end
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else if (cyc == 3) begin
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`checks(e.name, "ELARGE");
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`checkh(e.next, E01);
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`checkh(e.prev, E01);
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`checkh(e.next(0), ELARGE);
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`checkh(e.prev(0), ELARGE);
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e <= E01;
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end
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//
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else if (cyc == 10) begin
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i_cast <= $cast(e, 60'h1234);
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end
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else if (cyc == 11) begin
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`checkh(i_cast, 0);
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i_cast <= $cast(e, 60'h1);
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end
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else if (cyc == 12) begin
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`checkh(i_cast, 1);
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i_cast <= $cast(e, 60'h1234_4567_abcd);
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end
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else if (cyc == 13) begin
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`checkh(i_cast, 1);
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end
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//
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else if (cyc == 20) begin
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e <= my_t'('h11); // Unknown
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end
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else if (cyc == 21) begin
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`checks(e.name, ""); // Unknown
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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