forked from github/verilator
67 lines
1.5 KiB
Systemverilog
67 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum { EN_ZERO,
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EN_ONE
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} En_t;
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Insure that we can declare a type with a function declaration
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function enum integer {
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EF_TRUE = 1,
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EF_FALSE = 0 }
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f_enum_inv ( input a);
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f_enum_inv = a ? EF_FALSE : EF_TRUE;
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endfunction
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initial begin
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if (f_enum_inv(1) != 0) $stop;
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if (f_enum_inv(0) != 1) $stop;
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end
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En_t a, z;
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sub sub (/*AUTOINST*/
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// Outputs
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.z (z),
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// Inputs
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.a (a));
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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a <= EN_ZERO;
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end
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if (cyc==2) begin
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a <= EN_ONE;
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if (z != EN_ONE) $stop;
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end
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if (cyc==3) begin
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if (z != EN_ZERO) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module sub (input En_t a, output En_t z);
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always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
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endmodule
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// Local Variables:
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// verilog-typedef-regexp: "_t$"
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// End:
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