forked from github/verilator
14 lines
302 B
Systemverilog
14 lines
302 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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typedef enum bad_redecl [2:0] {
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VALUE
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} bad_redecl;
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endmodule
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