forked from github/verilator
47 lines
1.0 KiB
Systemverilog
47 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_embed1_child (/*AUTOARG*/
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// Outputs
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bit_out, vec_out, wide_out, did_init_out,
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// Inputs
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clk, bit_in, vec_in, wide_in, is_ref
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);
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input clk;
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input bit_in;
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output bit_out;
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input [30:0] vec_in;
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output logic [30:0] vec_out;
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input [123:0] wide_in;
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output logic [123:0] wide_out;
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output did_init_out;
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input is_ref;
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reg did_init; initial did_init = 0;
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initial begin
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did_init = 1;
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end
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reg did_final; initial did_final = 0;
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final begin
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did_final = 1;
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if (!is_ref) $write("*-* All Finished *-*\n");
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//$finish is in parent
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end
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// Note async use!
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wire bit_out = bit_in;
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wire did_init_out = did_init;
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always @ (posedge clk) begin
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vec_out <= vec_in;
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wide_out <= wide_in;
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end
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endmodule
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