forked from github/verilator
35 lines
915 B
Systemverilog
35 lines
915 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t (/*AUTOARG*/);
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byte dyn [][1:0];
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initial begin
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begin
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dyn = new [3];
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dyn[0] = '{101, 100};
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dyn[1] = '{111, 110};
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dyn[2] = '{121, 120};
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`ifndef verilator // bug2314
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`checkh(dyn[0][0], 100);
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`checkh(dyn[0][1], 101);
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`checkh(dyn[1][0], 110);
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`checkh(dyn[1][1], 111);
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`checkh(dyn[2][0], 120);
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`checkh(dyn[2][1], 121);
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`endif
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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