forked from github/verilator
28 lines
691 B
Systemverilog
28 lines
691 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t ();
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import "DPI-C" function int dpii_string(input string DSM_NAME);
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generate
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begin : DSM
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string SOME_STRING;
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end
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endgenerate
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initial begin
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$sformat(DSM.SOME_STRING, "%m");
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if (dpii_string(DSM.SOME_STRING) != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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