forked from github/verilator
41 lines
1.2 KiB
Systemverilog
41 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2020 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (/*AUTOARG*/);
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import "DPI-C" function void dpii_nullptr();
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// verilator lint_off UNDRIVEN
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int i_int_u3 [2:-2] [-3:3] [4:-4];
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import "DPI-C" function void dpii_int_u3(input int i [] [] []);
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real i_real_u1 [1:0];
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import "DPI-C" function void dpii_real_u1(input real i []);
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bit i_u6 [2][2][2][2][2][2];
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import "DPI-C" function void dpii_bit_u6(input bit i [][][][][][]);
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real i_real_u6 [2][2][2][2][2][2];
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import "DPI-C" function void dpii_real_u6(input real i [][][][][][]);
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initial begin
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i_int_u3[0][0][0] = 32'hbad;
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i_real_u1[0] = 1.1;
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i_u6[0][0][0][0][0][0] = 1'b1;
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dpii_nullptr();
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dpii_int_u3(i_int_u3);
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dpii_real_u1(i_real_u1);
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dpii_bit_u6(i_u6);
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dpii_real_u6(i_real_u6);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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