forked from github/verilator
23 lines
436 B
Systemverilog
23 lines
436 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`default_nettype none
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module t(
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input wire i,
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output wire o
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);
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logic a;
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logic b;
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initial begin
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a = 1'd0;
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b = 1'd0;
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end
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assign a = ~i;
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assign b = a;
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assign o = b;
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endmodule
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