forked from github/verilator
c9d6344f2f
A lot of optimizations in DFG assume a DAG, but the more things are representable, the more likely it is that a small cyclic sub-graph is present in an otherwise very large graph that is mostly acyclic. In order to avoid loosing optimization opportunities, we explicitly extract the cyclic sub-graphs (which are the strongly connected components + anything feeing them, up to variable boundaries) and treat them separately. This enables optimization of the remaining input.
45 lines
724 B
Systemverilog
45 lines
724 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off UNOPTFLAT
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module t (
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input wire i,
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output wire o
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);
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wire a;
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wire b;
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wire c;
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wire d;
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assign c = i + 1'b1;
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assign d = c + 1'b1;
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assign a = b + d;
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assign b = a + 1'b1;
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wire p;
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wire q;
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wire r;
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wire s;
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assign p = i + 1'b1;
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assign q = p + 1'b1;
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assign r = s ^ q;
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assign s = r + 1'b1;
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wire x;
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wire y;
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wire z;
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wire w;
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assign x = y ^ i;
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assign y = x;
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assign z = w;
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assign w = y & z;
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assign o = b | x;
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endmodule
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