forked from github/verilator
6ae6b16223
Folding an AstLogAnd with a non-zero constant operand used to coerce the type of the other operand, yielding an ill-typed node that DFG was then unhappy about. Add a RedOr instead if the width of the replacement operand is greater than zero. Fixes #3726
20 lines
345 B
Systemverilog
20 lines
345 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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x,
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// Inputs
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i
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);
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input i;
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output x;
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assign x = (i ? 0 : 1) && 1;
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endmodule
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