forked from github/verilator
39 lines
1010 B
Systemverilog
39 lines
1010 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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reg [31:0] dly0;
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// DFG can fold this into 'dly3 = dly1 = dly0 + 1' and 'dly2 = dly0 + 2',
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// but the 'dly0 + 1' term having multiple sinks needs to considered.
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wire [31:0] dly1 = dly0 + 32'h1;
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wire [31:0] dly2 = dly1 + 32'h1;
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wire [31:0] dly3 = dly0 + 32'h1;
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always @ (posedge clk) begin
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$display("[%0t] dly0=%h dly1=%h dly2=%h dly3=%h", $time, dly0, dly1, dly2, dly3);
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cyc <= cyc + 1;
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if (cyc == 1) begin
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dly0 <= 32'h55;
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end
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else if (cyc == 3) begin
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if (dly1 !== 32'h56) $stop;
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if (dly2 !== 32'h57) $stop;
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if (dly3 !== 32'h56) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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