forked from github/verilator
39 lines
768 B
Systemverilog
39 lines
768 B
Systemverilog
// DESCRIPTION: Verilator: Simple test of unoptflat
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Jie Xu.
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// SPDX-License-Identifier: CC0-1.0
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localparam ID_MSB = 1;
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module t (/*AUTOARG*/
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// Inputs
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clk,
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res
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);
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input clk;
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output [8:0][8:0] res;
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logic a = 1'b1;
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logic [8:0] b [8:0]; // where the error is reported
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logic [8:0][8:0] c; // where the error is reported
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// following just to make c as circular
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assign c[0] = c[0] | a << 1;
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assign b[0] = b[0] | a << 2;
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assign res[0] = c[0];
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assign res[1] = b[0];
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always @(posedge clk or negedge clk) begin
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if (res != 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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