forked from github/verilator
40 lines
2.2 KiB
Plaintext
40 lines
2.2 KiB
Plaintext
%Warning-ASSIGNDLY: t/t_delay.v:25:11: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... In instance t
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25 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
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| ^
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... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
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... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
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%Warning-ASSIGNDLY: t/t_delay.v:26:11: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... In instance t
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26 | assign #(sub.delay) dly3 = dly1 + 1;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:33:18: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... In instance t
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33 | dly0 <= #0 32'h11;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:36:18: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... In instance t
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36 | dly0 <= #0.12 dly0 + 32'h12;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:44:18: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... In instance t
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44 | dly0 <= #(dly_s.dly) 32'h55;
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| ^
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%Warning-STMTDLY: t/t_delay.v:50:10: Ignoring delay on this statement due to --no-timing
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: ... In instance t
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50 | #100 $finish;
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| ^
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%Warning-UNUSEDSIGNAL: t/t_delay.v:23:12: Signal is not used: 'dly_s'
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: ... In instance t
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23 | dly_s_t dly_s;
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| ^~~~~
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%Warning-UNUSEDSIGNAL: t/t_delay.v:57:13: Signal is not used: 'delay'
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: ... In instance t.sub
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57 | realtime delay = 2.3;
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| ^~~~~
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%Warning-BLKSEQ: t/t_delay.v:43:20: Blocking assignment '=' in sequential logic process
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: ... Suggest using delayed assignment '<='
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43 | dly_s.dly = 55;
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| ^
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%Error: Exiting due to
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