forked from github/verilator
125 lines
2.7 KiB
Systemverilog
125 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Dedupe optimization test.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// Contributed 2012 by Varun Koyyalagunta, Centaur Technology.
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//
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// Test consists of the follow logic tree, which has many obvious
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// places for dedupe:
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/*
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output
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+
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--------------/ \--------------
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/ \
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+ +
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----/ \----- ----/ \----
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/ + / +
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+ / \ + / \
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-/ \- a b -/ \- a b
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/ \ / \
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+ + + +
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/ \ / \ / \ / \
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a b c d a b c d
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*/
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module t(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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wire left,right;
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add add(sum,left,right,clk);
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l l(left,a,b,c,d,clk);
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r r(right,a,b,c,d,clk);
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endmodule
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module l(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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wire left, right;
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add add(sum,left,right,clk);
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ll ll(left,a,b,c,d,clk);
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lr lr(right,a,b,c,d,clk);
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endmodule
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module ll(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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wire left, right;
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add add(sum,left,right,clk);
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lll lll(left,a,b,c,d,clk);
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llr llr(right,a,b,c,d,clk);
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endmodule
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module lll(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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add add(sum,a,b,clk);
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endmodule
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module llr(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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add add(sum,c,d,clk);
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endmodule
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module lr(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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add add(sum,a,b,clk);
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endmodule
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module r(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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wire left, right;
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add add(sum,left,right,clk);
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rl rl(left,a,b,c,d,clk);
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rr rr(right,a,b,c,d,clk);
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endmodule
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module rr(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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add add(sum,a,b,clk);
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endmodule
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module rl(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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wire left, right;
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add add(sum,left,right,clk);
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rll rll(left,a,b,c,d,clk);
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rlr rlr(right,a,b,c,d,clk);
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endmodule
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module rll(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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add2 add(sum,a,b,clk);
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endmodule
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module rlr(sum,a,b,c,d,clk);
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output sum;
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input a,b,c,d,clk;
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add2 add(sum,c,d,clk);
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endmodule
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module add(sum,x,y,clk);
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output reg sum;
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input x,y,clk;
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reg t1,t2;
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always @(posedge clk) begin
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sum <= x + y;
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end
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endmodule
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module add2(sum,x,y,clk);
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output reg sum;
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input x,y,clk;
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reg t1,t2;
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always @(posedge clk) begin
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sum <= x + y;
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end
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endmodule
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