forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
63 lines
1.4 KiB
Systemverilog
63 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Dedupe optimization test.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// Contributed 2012 by Varun Koyyalagunta, Centaur Technology.
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module t(res,d,clk,en);
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output res;
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input d,en,clk;
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wire q0,q1,q2,q3;
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flop_gated_latch f0(q0,d,clk,en);
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flop_gated_latch f1(q1,d,clk,en);
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flop_gated_flop f2(q2,d,clk,en);
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flop_gated_flop f3(q3,d,clk,en);
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assign res = (q0 + q1) * (q2 - q3);
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endmodule
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module flop_gated_latch(q,d,clk,en);
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input d, clk, en;
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output reg q;
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wire gated_clock;
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clock_gate_latch clock_gate(gated_clock, clk, en);
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always @(posedge gated_clock) begin
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q <= d;
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end
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endmodule
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module flop_gated_flop(q,d,clk,en);
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input d, clk, en;
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output reg q;
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wire gated_clock;
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clock_gate_flop clock_gate(gated_clock, clk, en);
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always @(posedge gated_clock) begin
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q <= d;
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end
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endmodule
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module clock_gate_latch (gated_clk, clk, clken);
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output gated_clk;
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input clk, clken;
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reg clken_latched;
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assign gated_clk = clk & clken_latched ;
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wire clkb = ~clk;
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always_latch @(clkb or clken)
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if(clkb) clken_latched = clken;
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endmodule
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module clock_gate_flop (gated_clk, clk, clken);
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output gated_clk;
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input clk, clken;
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reg clken_r;
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assign gated_clk = clk & clken_r ;
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always @(negedge clk)
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clken_r <= clken;
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endmodule
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