forked from github/verilator
61 lines
1.4 KiB
Systemverilog
61 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg toggle;
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integer cyc; initial cyc=1;
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Test suba (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc (cyc[31:0]));
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Test subb (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc (cyc[31:0]));
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Test subc (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.toggle (toggle),
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.cyc (cyc[31:0]));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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toggle <= !cyc[0];
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if (cyc==9) begin
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end
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test
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(
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input clk,
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input toggle,
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input [31:0] cyc
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);
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// Don't flatten out these modules please:
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// verilator no_inline_module
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// Labeled cover
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cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
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endmodule
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