forked from github/verilator
37 lines
976 B
Systemverilog
37 lines
976 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [31:0] arr [0:7];
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assign arr[0:7] = {
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{16'hffff, 16'h0000},
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{16'h0000, 16'h0000},
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{16'h0a0a, 16'h0000},
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{16'ha0a0, 16'h0000},
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{16'hffff, 16'h0000},
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{16'h0000, 16'h0000},
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{16'h0a0a, 16'h0000},
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{16'ha0a0, 16'h0000}
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};
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 9) begin
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if (arr[0] !== 32'hffff0000) $stop;
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if (arr[7] !== 32'ha0a00000) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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