forked from github/verilator
91 lines
2.6 KiB
Systemverilog
91 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 10ns/1ns
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`ifdef TEST_VERBOSE
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`define WRITE_VERBOSE(args) $write args
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`else
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`define WRITE_VERBOSE(args)
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`endif
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`ifndef TEST_WIDTH
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`define TEST_WIDTH 4
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`endif
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`ifndef TEST_BITS
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`define TEST_BITS 4*`TEST_WIDTH
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`endif
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`ifndef TEST_CLK_PERIOD
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`define TEST_CLK_PERIOD 10
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`endif
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`ifndef TEST_INPUT_SKEW
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`define TEST_INPUT_SKEW 2
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`endif
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`ifndef TEST_OUTPUT_SKEW
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`define TEST_OUTPUT_SKEW 6
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`endif
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`ifndef TEST_CYCLE_DELAY
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`define TEST_CYCLE_DELAY 4
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`endif
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module t;
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typedef logic[`TEST_BITS-1:0] sig_t;
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sig_t D, Q;
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always @(posedge clk) Q <= D;
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logic clk = 0;
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always #(`TEST_CLK_PERIOD/2) clk = ~clk;
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always @(posedge clk) `WRITE_VERBOSE(("[%0t] posedge clk\n", $time));
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default clocking cb @(posedge clk);
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default input #`TEST_INPUT_SKEW output #`TEST_OUTPUT_SKEW;
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input Q;
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output D;
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endclocking
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`ifdef TEST_VERBOSE
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initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, D, Q, cb.Q);
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`endif
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always
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begin
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sig_t val = '0;
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cb.D <= val;
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for (int i = 0; i < 5; i++) begin ##(`TEST_CYCLE_DELAY+`TEST_OUTPUT_SKEW/`TEST_CLK_PERIOD+1)
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val = {`TEST_WIDTH{(`TEST_BITS/`TEST_WIDTH)'('ha + i)}};
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`WRITE_VERBOSE(("[%0t] cb.D <= ##%0d %x\n", $time, `TEST_CYCLE_DELAY, val));
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cb.D <= ##(`TEST_CYCLE_DELAY) val;
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fork
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#(`TEST_CYCLE_DELAY*`TEST_CLK_PERIOD+`TEST_OUTPUT_SKEW-0.1) begin
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if (D == val) begin
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`WRITE_VERBOSE(("[%0t] D == %x == %x\n", $time, D, val));
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$stop;
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end
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if (cb.Q != D) begin
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`WRITE_VERBOSE(("[%0t] cb.Q == %x != %x\n", $time, cb.Q, D));
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$stop;
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end
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end
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#(`TEST_CYCLE_DELAY*`TEST_CLK_PERIOD+`TEST_OUTPUT_SKEW+0.1) begin
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if (D != val) begin
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`WRITE_VERBOSE(("[%0t] D == %x != %x\n", $time, D, val));
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$stop;
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end
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if (cb.Q == D) begin
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`WRITE_VERBOSE(("[%0t] cb.Q == %x == %x\n", $time, cb.Q, D));
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$stop;
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end
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end
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join_none
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end
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##4
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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