forked from github/verilator
38 lines
922 B
Systemverilog
38 lines
922 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic[3:0] D1, D2, Q1, Q2;
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always @(posedge clk) begin
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{Q1, Q2} <= {D1, D2};
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end
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always @(posedge clk) $display("[%0t] posedge clk", $time);
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clocking cb @(posedge clk);
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input #0 Q = {Q1, Q2};
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output #0 D = {D1, D2};
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endclocking
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initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, {D1,D2}, {Q1,Q2}, cb.Q);
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int cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc > 1 && cb.Q != {D1 - 4'd1, D2 - 4'd1}) $stop;
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cb.D <= {D1 + 4'd1, D2 + 4'd1};
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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