forked from github/verilator
35 lines
656 B
Systemverilog
35 lines
656 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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sub sub(.*);
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// Bad - no global clock
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always @ ($global_clock) $display;
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endmodule
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module sub(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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global clocking ck @(posedge clk); endclocking
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// Bad - global duplicate
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global clocking ogck @(posedge clk); endclocking
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// Bad - name duplicate
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global clocking ck @(posedge clk); endclocking
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endmodule
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