forked from github/verilator
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
60 lines
1.1 KiB
Systemverilog
60 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Simple test of CLkDATA
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//
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// Trigger the CLKDATA detection
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Jie Xu.
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// SPDX-License-Identifier: CC0-1.0
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localparam ID_MSB = 1;
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module t (/*AUTOARG*/
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// Inputs
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clk,
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res,
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res8,
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res16
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);
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input clk;
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output reg res;
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// When not inlining the below may trigger CLKDATA
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output reg [7:0] res8;
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output reg [15:0] res16;
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wire [7:0] clkSet;
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wire clk_1;
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wire [2:0] clk_3;
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wire [3:0] clk_4;
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wire clk_final;
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reg [7:0] count;
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assign clkSet = {8{clk}};
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assign clk_4 = clkSet[7:4];
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assign clk_1 = clk_4[0];;
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// arraysel
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assign clk_3 = {3{clk_1}};
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assign clk_final = clk_3[0];
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assign res8 = {clk_3, 1'b0, clk_4};
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assign res16 = {count, clk_3, clk_1, clk_4};
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initial
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count = 0;
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always @(posedge clk_final or negedge clk_final) begin
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count = count + 1;
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res <= clk_final;
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if ( count == 8'hf) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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