forked from github/verilator
33 lines
1.3 KiB
Perl
Executable File
33 lines
1.3 KiB
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_clk_concat.v");
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my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml";
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compile(
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verilator_flags2 => ["t/t_clk_concat.vlt"],
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);
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if ($Self->{vlt_all}) {
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file_grep("$out_filename", qr/\<var loc="f,78,.*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
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file_grep("$out_filename", qr/\<var loc="f,79,.*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
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file_grep("$out_filename", qr/\<var loc="f,80,.*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
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file_grep("$out_filename", qr/\<var loc="f,82,.*?" name="data_in" .*dir="input" .*vartype="logic" origName="data_in" clocker="false" public="true"\/\>/i);
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}
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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