forked from github/verilator
48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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virtual interface vi_t vi;
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virtual vi_t vi2;
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typedef class c;
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typedef interface class ic;
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class C #(parameter P=1);
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localparam LOCPAR = 10;
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int imember;
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static int istatic;
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local int loc;
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protected int prot;
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rand int irand;
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randc int icrand;
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task classtask; endtask
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function int classfunc; endfunction
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virtual function void func_virtual; endfunction
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pure virtual function void func_pure_virtual;
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automatic function void func_automatic; endfunction
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const function void func_const; endfunction
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extern task exttask;
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endclass
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virtual class VC;
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endclass
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module t (/*AUTOARG*/);
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endmodule
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typedef class uvm_root;
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typedef class uvm_coreservice_t;
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class uvm_default_coreservice_t extends uvm_coreservice_t;
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virtual function uvm_root get_root();
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uvm_root::m_forward_task_call();
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return uvm_root::m_uvm_get_root();
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endfunction
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endclass
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