forked from github/verilator
119 lines
3.1 KiB
Systemverilog
119 lines
3.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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// See also t_class_param.v
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module t (/*AUTOARG*/);
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class Cls #(parameter PBASE = 12);
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bit [PBASE-1:0] member;
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function bit [PBASE-1:0] get_member;
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return member;
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endfunction
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static function int get_p;
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return PBASE;
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endfunction
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typedef enum { E_PBASE = PBASE } enum_t;
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endclass
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class Wrap #(parameter P = 13);
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function int get_p;
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return c1.get_p();
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endfunction
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function new;
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c1 = new;
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endfunction
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Cls#(PMINUS1 + 1) c1;
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localparam PMINUS1 = P - 1; // Checking works when last
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endclass
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class Wrap2 #(parameter P = 35);
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function int get_p;
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return c1.get_p();
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endfunction
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function new;
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c1 = new;
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endfunction
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Wrap#(PMINUS1 + 1) c1;
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localparam PMINUS1 = P - 1; // Checking works when last
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endclass
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typedef Cls#(8) Cls8_t;
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class SelfRefClassTypeParam #(type T=logic);
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typedef SelfRefClassTypeParam #(int) self_int_t;
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T field;
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endclass
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class SelfRefClassIntParam #(int P=1);
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typedef SelfRefClassIntParam #(10) self_int_t;
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endclass
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Cls c12;
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Cls #(.PBASE(4)) c4;
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Cls8_t c8;
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Wrap #(.P(16)) w16;
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Wrap2 #(.P(32)) w32;
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SelfRefClassTypeParam src_logic;
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SelfRefClassTypeParam::self_int_t src_int;
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SelfRefClassIntParam src1;
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SelfRefClassIntParam::self_int_t src10;
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initial begin
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c12 = new;
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c4 = new;
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c8 = new;
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w16 = new;
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w32 = new;
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src_int = new;
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src_logic = new;
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src1 = new;
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src10 = new;
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if (Cls#()::PBASE != 12) $stop;
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if (Cls#(4)::PBASE != 4) $stop;
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if (Cls8_t::PBASE != 8) $stop;
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if (Cls#()::E_PBASE != 12) $stop;
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if (Cls#(4)::E_PBASE != 4) $stop;
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if (Cls8_t::E_PBASE != 8) $stop;
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if (c12.PBASE != 12) $stop;
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if (c4.PBASE != 4) $stop;
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if (c8.PBASE != 8) $stop;
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if (Cls#()::get_p() != 12) $stop;
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if (Cls#(4)::get_p() != 4) $stop;
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if (Cls8_t::get_p() != 8) $stop;
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if (c12.get_p() != 12) $stop;
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if (c4.get_p() != 4) $stop;
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if (c8.get_p() != 8) $stop;
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if (w16.get_p() != 16) $stop;
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if (w32.get_p() != 32) $stop;
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// verilator lint_off WIDTH
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c12.member = 32'haaaaaaaa;
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c4.member = 32'haaaaaaaa;
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c8.member = 32'haaaaaaaa;
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// verilator lint_on WIDTH
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if (c12.member != 12'haaa) $stop;
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if (c4.member != 4'ha) $stop;
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if (c12.get_member() != 12'haaa) $stop;
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if (c4.get_member() != 4'ha) $stop;
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`checks($sformatf("%p", c12), "'{member:'haaa}");
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`checks($sformatf("%p", c4), "'{member:'ha}");
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if ($bits(src_logic.field) != 1) $stop;
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if ($bits(src_int.field) != 32) $stop;
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if (src1.P != 1) $stop;
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if (src10.P != 10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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