forked from github/verilator
90 lines
2.1 KiB
Systemverilog
90 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Let context messages easily know if given line is expected ok or bad
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task ok;
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endtask
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task bad;
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endtask
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class Cls;
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int m_pub = 1;
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local int m_loc = 2;
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protected int m_prot = 3;
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task f_pub; endtask
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local task f_loc; endtask
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protected task f_prot; endtask
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static task s_pub; endtask
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static local task s_loc; endtask
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static protected task s_prot; endtask
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task check;
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Cls o;
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ok(); if (m_pub != 1) $stop;
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ok(); if (m_loc != 10) $stop;
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ok(); if (m_prot != 20) $stop;
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ok(); f_pub();
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ok(); f_loc();
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ok(); f_prot();
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ok(); o.f_pub();
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ok(); o.f_loc();
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ok(); o.f_prot();
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ok(); s_pub();
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ok(); s_loc();
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ok(); s_prot();
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ok(); Cls::s_pub();
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ok(); Cls::s_loc();
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ok(); Cls::s_prot();
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endtask
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endclass
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class Ext extends Cls;
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task check;
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Ext o;
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ok(); if (m_pub != 1) $stop;
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bad(); if (m_loc != 10) $stop;
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ok(); if (m_prot != 20) $stop;
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ok(); f_pub();
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bad(); f_loc();
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ok(); f_prot();
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ok(); o.f_pub();
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bad(); o.f_loc();
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ok(); o.f_prot();
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ok(); s_pub();
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bad(); s_loc();
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ok(); s_prot();
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ok(); Cls::s_pub();
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bad(); Cls::s_loc();
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ok(); Cls::s_prot();
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endtask
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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Ext e;
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c = new;
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e = new;
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ok(); if (c.m_pub != 1) $stop;
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bad(); if (c.m_loc != 2) $stop;
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bad(); if (c.m_prot != 20) $stop;
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ok(); if (e.m_pub != 1) $stop;
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bad(); if (e.m_loc != 2) $stop;
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bad(); if (e.m_prot != 20) $stop;
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ok(); c.f_pub();
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bad(); c.f_loc();
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bad(); c.f_prot();
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ok(); c.s_pub();
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bad(); c.s_loc();
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bad(); c.s_prot();
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ok(); Cls::s_pub();
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bad(); Cls::s_loc();
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bad(); Cls::s_prot();
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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