forked from github/verilator
73 lines
1.5 KiB
Systemverilog
73 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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typedef enum {A = 10, B = 20, C = 30} en_t;
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int m_pub = 1;
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local int m_loc = 2;
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protected int m_prot = B;
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task f_pub; endtask
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local task f_loc; endtask
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protected task f_prot; endtask
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static task s_pub; endtask
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static local task s_loc; endtask
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static protected task s_prot; endtask
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task check;
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Cls o;
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if (m_pub != 1) $stop;
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if (m_loc != 2) $stop;
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if (m_prot != 20) $stop;
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f_pub(); // Ok
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f_loc(); // Ok
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f_prot(); // Ok
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s_pub(); // Ok
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s_loc(); // Ok
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s_prot(); // Ok
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Cls::s_pub(); // Ok
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Cls::s_loc(); // Ok
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Cls::s_prot(); // Ok
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endtask
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endclass
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class Ext extends Cls;
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task check;
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if (m_pub != 1) $stop;
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if (m_prot != 20) $stop;
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f_pub(); // Ok
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f_prot(); // Ok
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s_pub(); // Ok
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s_prot(); // Ok
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Cls::s_pub(); // Ok
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Cls::s_prot(); // Ok
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endtask
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endclass
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module t (/*AUTOARG*/);
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const Cls mod_c = new;
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initial begin
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Cls c;
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Ext e;
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if (c.A != 10) $stop;
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c = new;
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e = new;
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if (c.m_pub != 1) $stop;
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//
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if (mod_c.A != 10) $stop;
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//
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c.check();
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e.check();
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//
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Cls::s_pub(); // Ok
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c.s_pub(); // Ok
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e.s_pub(); // Ok
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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