forked from github/verilator
41 lines
929 B
Systemverilog
41 lines
929 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package P;
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typedef class ClsB;
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class ClsA;
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int imembera;
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ClsB b;
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endclass
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class ClsB;
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int imemberb;
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ClsA a;
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endclass
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endpackage
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module t (/*AUTOARG*/);
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P::ClsA ca;
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P::ClsB cb;
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initial begin
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// Alternate between two versions to make sure we don't
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// constant propagate between them.
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ca = new;
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cb = new;
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ca.b = new;
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cb.a = new;
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ca.imembera = 100;
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ca.b.imemberb = 111;
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cb.imemberb = 200;
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cb.a.imembera = 202;
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if (ca.imembera != 100) $stop;
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if (ca.b.imemberb != 111) $stop;
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if (cb.imemberb != 200) $stop;
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if (cb.a.imembera != 202) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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