forked from github/verilator
51 lines
1.0 KiB
Systemverilog
51 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int value;
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extern function int ext_f_np;
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extern function int ext_f_p();
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extern function int ext_f_i(int in);
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extern task ext_t_np;
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extern task ext_t_p();
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extern task ext_t_i(int in);
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endclass
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function int Cls::ext_f_np;
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return 1;
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endfunction
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function int Cls::ext_f_p();
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return value;
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endfunction
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function int Cls::ext_f_i(int in);
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return in+1;
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endfunction
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task Cls::ext_t_np();
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$write("*-* All Finished *-*\n");
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endtask
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task Cls::ext_t_p();
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$finish;
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endtask
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task Cls::ext_t_i(int in);
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if (in != 2) $stop;
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value = in;
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endtask
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module t (/*AUTOARG*/);
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initial begin
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Cls c = new;
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c.ext_t_i(2);
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c.ext_t_np();
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c.ext_t_p();
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if (c.ext_f_np() != 1) $stop;
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if (c.ext_f_p() != 2) $stop;
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if (c.ext_f_i(10) != 11) $stop;
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end
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endmodule
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