forked from github/verilator
60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Base0;
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// No members to check that to_string handles this
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endclass
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class Base1 extends Base0;
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int b1member;
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typedef int T;
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endclass
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class Base2 extends Base1;
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int b2member;
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endclass
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class Cls extends Base2;
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int imembera;
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int imemberb;
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T imemberc;
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endclass : Cls
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class uvm_object_wrapper;
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function int create ();
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endfunction
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endclass
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class uvm__registry #(type T=int) extends uvm_object_wrapper;
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// This override must be in the new symbol table, not
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// under the extend's symbol table
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function int create ();
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T obj;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.b1member = 10;
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c.b2member = 30;
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c.imembera = 100;
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c.imemberb = 110;
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c.imemberc = 120;
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$display("Display: set = \"%p\"", c); // '{all 4 members}
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if (c.b1member != 10) $stop;
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if (c.b2member != 30) $stop;
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if (c.imembera != 100) $stop;
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if (c.imemberb != 110) $stop;
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if (c.imemberc != 120) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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