forked from github/verilator
68927d4fd3
Prevents the possibility of assigning an integer to a class reference, both at the SystemVerilog and the emitted C++ levels. Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
22 lines
386 B
Systemverilog
22 lines
386 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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endclass : Cls
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module t (/*AUTOARG*/);
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Cls c;
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task t(Cls c); endtask
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initial begin
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c = 0;
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c = 1;
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t(0);
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t(1);
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end
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endmodule
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