forked from github/verilator
31 lines
610 B
Systemverilog
31 lines
610 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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endclass
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class BaseExtended extends Base;
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endclass
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class Other;
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endclass
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typedef Base Base_t;
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typedef BaseExtended BaseExtended_t;
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typedef Other Other_t;
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module t;
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Base_t cls_a;
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BaseExtended_t cls_ab;
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Other_t other;
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initial begin
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cls_a = new;
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cls_ab = BaseExtended'(cls_a); // bad-need dyn
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other = Other'(cls_ab); // bad-incompat
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end
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endmodule
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