forked from github/verilator
132 lines
3.6 KiB
Systemverilog
132 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface intf;
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typedef logic [7:0] octet;
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typedef octet [1:0] word;
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octet [1:0] octets;
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word [1:0] words;
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endinterface
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module t;
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typedef logic [3:0] mc_t;
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typedef mc_t tocast_t;
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typedef logic [2:0] [7:0] two_dee_t;
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typedef struct packed {
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logic [15:0] data;
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} packed_t;
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typedef struct packed {
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logic [31:0] data;
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} packed2_t;
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typedef enum [15:0] {
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ONE = 1
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} enum_t;
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packed_t pdata;
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packed_t pdata_reg;
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packed2_t pdata2_reg;
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assign pdata.data = 16'h1234;
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logic [7:0] logic8bit;
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assign logic8bit = $bits(logic8bit)'(pdata >> 8);
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mc_t o;
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enum_t e;
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intf the_intf();
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logic [15:0] allones = 16'hffff;
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parameter FOUR = 4;
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localparam two_dee_t two_dee = two_dee_t'(32'habcdef);
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// bug925
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localparam [6:0] RESULT = 7'((6*9+92)%96);
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logic signed [14:0] samp0 = 15'h0000;
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logic signed [14:0] samp1 = 15'h0000;
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logic signed [14:0] samp2 = 15'h6000;
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logic signed [11:0] coeff0 = 12'h009;
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logic signed [11:0] coeff1 = 12'h280;
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logic signed [11:0] coeff2 = 12'h4C5;
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logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11));
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// verilator lint_off WIDTH
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logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
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// verilator lint_on WIDTH
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logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
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(27'(coeff1 * samp1) >>> 11) +
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(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
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logic one = 1'b1;
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logic [32:0] b33 = {32'(0), one};
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logic [31:0] b32 = {31'(0), one};
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logic [31:0] thirty_two_bits;
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two_dee_t two_dee_sig;
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initial begin
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if (logic8bit != 8'h12) $stop;
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if (4'shf > 4'sh0) $stop;
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if (signed'(4'hf) > 4'sh0) $stop;
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if (4'hf < 4'h0) $stop;
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if (unsigned'(4'shf) < 4'h0) $stop;
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if (const'(4'shf) !== 4'shf) $stop;
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if (4'(allones) !== 4'hf) $stop;
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if (6'(allones) !== 6'h3f) $stop;
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if ((4)'(allones) !== 4'hf) $stop;
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if ((4+2)'(allones) !== 6'h3f) $stop;
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if ((4-2)'(allones) !== 2'h3) $stop;
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if ((FOUR+2)'(allones) !== 6'h3f) $stop;
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if (50 !== RESULT) $stop;
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e = ONE;
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if (e != 1) $stop;
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if (e != ONE) $stop;
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e = enum_t'(ONE);
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if (e != ONE) $stop;
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e = enum_t'(16'h1);
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if (e != ONE) $stop;
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pdata_reg.data = 1;
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e = enum_t'(pdata_reg);
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if (e != ONE) $stop;
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o = tocast_t'(4'b1);
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if (o != 4'b1) $stop;
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the_intf.octets = 16'd1;
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pdata_reg = packed_t'(the_intf.octets);
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if (pdata_reg.data != 16'd1) $stop;
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the_intf.words = 32'd1;
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pdata2_reg = packed2_t'(the_intf.words);
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if (pdata2_reg.data != 32'd1) $stop;
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if (15'h6cec != outa) $stop;
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if (27'h7ffecec != mida) $stop;
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if (27'h7ffecec != midb) $stop;
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if (b33 != 33'b1) $stop;
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if (b32 != 32'b1) $stop;
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if (two_dee[0] != 8'hef) $stop;
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if (two_dee[1] != 8'hcd) $stop;
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if (two_dee[2] != 8'hab) $stop;
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thirty_two_bits = 32'h123456;
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two_dee_sig = two_dee_t'(thirty_two_bits);
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if (two_dee_sig[0] != 8'h56) $stop;
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if (two_dee_sig[1] != 8'h34) $stop;
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if (two_dee_sig[2] != 8'h12) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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