forked from github/verilator
30 lines
516 B
Systemverilog
30 lines
516 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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enum logic [2:0] {
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e0,
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e1,
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e2,
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e3
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} EN;
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initial begin
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unique case (EN)
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e0 :;
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e1 :;
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e2 :;
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e3 :;
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endcase
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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