forked from github/verilator
43 lines
798 B
Systemverilog
43 lines
798 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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always @(*) begin
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if (clk) begin end
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end
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always @(* ) begin
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if (clk) begin end
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end
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// Not legal in some simulators, legal in others
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// always @(* /*cmt*/ ) begin
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// if (clk) begin end
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// end
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// Not legal in some simulators, legal in others
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// always @(* // cmt
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// ) begin
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// if (clk) begin end
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// end
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always @ (*
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) begin
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if (clk) begin end
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end
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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