forked from github/verilator
49 lines
1.4 KiB
Systemverilog
49 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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int imap[int];
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// associative array of an associative array
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logic [31:0] a [logic [31:0]][logic [63:0]];
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task static disp();
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int i = 60;
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imap[i++] = 600;
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imap[i++] = 601;
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foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]);
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endtask
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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a[5][8] = 8;
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a[5][9] = 9;
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imap[10] = 100;
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imap[11] = 101;
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end
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else if (cyc == 2) begin
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`checkh(a[5][8], 8);
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`checkh(a[5][9], 9);
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disp();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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